assembly - memory adressing on intel ia 32 -

i know memory addressing can done multiples of word size intel 32 bits, allocating memory on stack in assembly can done

    //pseudo code     sub , esp ,4 // allocating integer on stack     sub esp, 8 // buffer of size 5 example b[5]  

so addressing done multiples of 4's. referring locals , parameters on stack done with

     // referring variable --ebp-4 

but in disassembly see instructions like

     movb   $0x41, 0xffffffff(%ebp)   ,// refer ebp-1 example 

so refers memory 1 bytes.

so refers 1 byte, not multiple of 4 bytes.the multiple of 4 bytes esp? or related every register?

the multiple of 4 bytes esp? or related every register?

note that

sub esp, n

doesn't access memory location, use related memory alignment instruction simple register-immediate subtraction, it use value.

for performance reason if read 16 bits should on address multiple of 2, 32 bits should on address multiple of 4.
called natural boundary alignment.

32 bits systems can push/pop 16 or 32 bits values, if use multiple of 4 in instructions sub esp, n, push/pop access data aligned on natural boundaries (note 4 multiple of 2).

data on stack accessed directly instructions like

mov [ebp-04h], eax

the principle here same, ebp multiple of 4 (note value old esp value, before subtraction) 32 bits data stored in address multiple of 4 (naturally aligned).

the natural alignment of bytes is... 1. meaning should @ address multiple of 1, i.e. everywhere.
that's why mov [ebp-01h], 'a' performs mov [ebp-04h], 'a'.

---

_trivia

_{rule of thumbs ia32e general purpose instructions can read/write bytes qwords @ every address.
whole alignment story performance reasons, unlike risc machines cannot structurally access unaligned data.}

_{when introduced sse instructions came fast "aligned" (like movaps) , slow "unaligned" (like movups) versions of same instruction.}

_{64 bits systems explicitly require 128 bits alignment of stack better perform vector instructions (and widened registers).}

_{cpu has bit in eflags register, bit ac, let program enable or disable strict alignment policy (à la risc), supposed os has enabled feature (setting am in cr0).}

_{aligning data more strictly cpu data bus (for whatever definition of on modern integrated dram controller) pointless.
that's why new abis align on 128 bits cpu can have 512 bits registers.}

_{alignment requirement every instruction can found on manual 2 (the complete set).}